1. Technical Field
The various embodiments described herein are related to Application Specific Integrated Circuits (ASICs), and more particularly to the design of various ASICs.
2. Related Art
Contemporary digital ASIC designs are usually based on a synchronous paradigm. They rely on the availability of a periodic global control signal, typically called clock, that controls the sequential logic of an ASIC. In this way, time is perceived as a discrete variable governed by the clock signal therefor sequencing and control of events happen only on predictive points in time. Such discretization of time enables designers to ignore wire and gate delays while designing a digital ASIC; provided that a few timing constraints related to the clock signal are fulfilled. Such simplification is one of the key reasons behind the popularity of the synchronous paradigm.
However, in modern technologies, synchronous designs' timing constraints are becoming very difficult to meet, as process and on chip variation effects get more aggressive and performance, area and power budgets get tighter. To cope with such problems, there is a slow yet steady movement towards the adoption of non-synchronous techniques and better design space of the asynchronous paradigm. In fact, more and more designs are moving towards architectures with multiple clock islands and in some cases the adoption of fully asynchronous techniques. These techniques remove partially or completely the clock signal, using handshake protocols for control and sequencing of events instead. To do so, there are different approaches available in the state-of-the-art, including Bundled-Data circuits for Intellectual Property (IP) design and Chronos Channels for chip-level global communication.
Bundled-Data circuits comprise single-rail logic and conventional Boolean gates for combinatorial logic and, typically, conventional latch or flip-flop based circuits for sequential logic. This way, they can be implemented using conventional EDA tools and flows. Moreover, timing constraints and global signals distribution can be relaxed, potentially enabling savings in area and power. Yet, such circuits still need to be verified in every corner, as they rely on relative timing constraints for correct operation. Chronos Channels are advantageous because they are robust to Pressure, Volume and Temperature (PVT) variations and present no relative timing constraint. This way they alleviate timing closure of large chips by eliminating the need of verifying all constraints for Chronos Channel logic blocks. Also, they rely on temporal compression to potentially reduce area and power overheads. However, they rely on synchronizers to interface with synchronous IP blocks. Moreover, they rely on quasi-delay-insensitive logic to implement transmitter (TX) and receiver (RX) blocks, which, typically, consumes more area than bundled-data solutions. Chronos Channels are described in the U.S. patent applications incorporated above.